| Zugriffsnummer | 11396 |
| Dokumenttyp | Konferenzartikel |
| Sprache | Englisch |
| Titel | Digital correction of circuit imperfections in the 1-1-1 cascaded Σ-Δ modulator |
| Autor(in); Institution |
Davis, Alan J.; University of Rhode Island, Kingston, Rhode Island, USA
Fischer, Godi; University of Rhode Island, Kingston, Rhode Island, USA
Albrecht, Hans-Helge; 8.32, Messdatenerfassung und -übertragungstechnik, PTB-Berlin
Hess, Jürgen; 8.32, Messdatenerfassung und -übertragungstechnik, PTB-Berlin
|
| Quelle/Jahr | IWADC '99 : 4th International Workshop on ADC Modelling and Testing, September 9 - 10, 1999:(1999), 153 - 158 |
| Herausgeber(in) |
Marchegay, P.
Dallet, D.
|
| Verlag | Bordeaux: Ecole Nationale Superior d'Electricite et de Radiolelectricite |
| Konferenzangaben | 4th International Workshop on ADC Modelling and Testing, Bordeaux, September, 9-10, 1999, France |
| Freie Schlagworte | MASH ; Cascaded Sigma-Delta Modulator |
| Zusammenfassung | An approach to remove the effects of amplifier finite gain and C-ratio mismatches in the 1-1-1 cascade (MASH) sigma-delta modulator is presented. By correcting the digital outputs with estimates of the parasitic errors due to analog circuit imperfections the residual, intermediate quantization noise terms are attenuated allowing the SNDR to approach 106.7 dB, the performance of an ideal third-order modulator, for amplifier gain values as low as 400. A MASH modulator, implemented as a fully differential switched-capacitor circuit, has been fabricated in a 2.0µm double-poly n-well CMOS process. Measurements of the MASH verify that the error correction can restore a signal level of 40 µVolts with a positive SNDR for an amplifier gain of 59.6 dB, C-Ratio mismatch errors of -0.88% and -4.2% at an OSR of 64. |
