| Zugriffsnummer | 11252 |
| Dokumenttyp | Zeitschriftenartikel |
| Sprache | Englisch |
| Titel | Margins of junction parameter spread for non-hysteretic Josephson junction arrays |
| Autor(in); Institution |
Kim, Kyu-Tae; Korea Research Institute of Standards and Science, Daejeon, KOREA
Behr, Ralf; 2.6, Elektrische Einheiten, PTB-Braunschweig
Müller, Franz; 2.4, Quantenelektronik, PTB-Braunschweig
|
| Quelle/Jahr | Superconductor Science and Technology: 16 (2003), 12, 1344 - 1348 |
| ISSN | 0953-2048 |
| URL | |
| Verlag | Bristol: Institute of Physics Publishing Ltd |
| Zusammenfassung | The programmable Josephson voltage standard shows robust step stability and is convenient for many metrological applications. The advantages of the programmable Josephson voltage standard are due to the array of non-hysteretic Josephson junctions with very high uniformity. We have numerically investigated the non-hysteretic Josephson junction arrays: externally shunted SIS (superconductor-insulator-superconductor) junctions and SINIS (superconductor-insulator-normal metal-insulator-superconductor) junction array. For the externally shunted SIS junction, we found the existence of an optimal range of the the shunt inductance. For the SINIS junction array, the maximum tolerable nonuniformity of the junction parameters and the microwave power could be derived according to a tolerance criterion given in terms of the step width of the first Shapiro step. The simulation was also compared with an experimental observation for 1 V SINIS array with 8192 junctions. |
